1. Field of the Invention
The present invention relates to a PWM (Pulse Width Modulation) controller, and more particularly to a PWM controller capable of performing power management in power conversion applications.
2. Description of the Related Art
To describe the related art of the present invention, the relation between a PWM controller and a power conversion application shall be introduced first. Please refer to FIG. 1, which shows the architecture of a typical application of PWM controller. As shown in FIG. 1, the architecture realizing a fly-back type power converter, at least includes: a PWM controller 100, an input rectifier and filter 101, a main transformer 102, an output rectifier and filter 103, a feedback network 104, and an NMOS transistor 105.
In the architecture, the PWM controller 100 is used for generating a pulse signal SP in response to a feedback signal VFB.
The input rectifier and filter 101 is used for generating a first DC voltage according to an AC input power source.
The main transformer 102 and the output rectifier and filter 103 are used to transfer the first DC voltage to a DC output voltage VO.
The feedback network 104 is used to generate the feedback signal VFB according to the DC output voltage VO.
The NMOS transistor 105 is used to control the power transformation through the main transformer 102 in response to the pulse signal SP.
Through a periodic on-and-off switching of the NMOS transistor 105, which is driven by the pulse signal SP generated from the PWM controller 100, the input power is transformed through the main transformer 102 to the output. The operating principle of the PWM controller 100 is to be illustrated according to FIG. 2, which shows the circuit diagram of a prior art PWM controller. As shown in FIG. 2, the prior art PWM controller at least includes: a saw-tooth signal generator 200, a trigger generator 201, a latch 202, a NOT gate 203, a NOT gate 204, a reset generator 205 and an output stage 206.
In the circuit, the saw-tooth signal generator 200 is used for generating a saw-tooth signal VSAW in response to an ICKB signal and an ICK signal, and comprises a current source IUP, a switch SWUP, a capacitor CT, a switch SWDN and a current source IDN. When the switch SWUP is on, the current source IUP flowing into the capacitor CT will cause the saw-tooth signal VSAW to ramp up; when the switch SWDN is on, the current source IDN flowing out from the capacitor CT will cause the saw-tooth signal VSAW to ramp down.
The trigger generator 201 is used to generate a pair of trigger signals for the latch 202 according to the comparisons of the saw-tooth signal VSAW to a level VH and a level VL.
The latch 202 is used for generating a CKB signal and a CK signal according to the pair of trigger signals, in which the CKB signal is a complement to the CK signal.
The NOT gate 203 is used to generate the ICKB signal according to the CKB signal; the NOT gate 204 is used to generate the ICK signal according to the CK signal.
The reset generator 205 is used for generating a RESET signal according to a ramp signal VS and a V+ signal which is derived from the feedback signal VFB. When the RESET signal is at low logic level, the pulse signal SP of the output stage 206 will be pulled down to low logic level and the NMOS transistor 105 (shown in FIG. 1) will therefore be turned off.
The output stage 206 is used to generate the pulse signal SP in response to the CK signal and the RESET signal. The timing relation among the saw-tooth signal VSAW, CKB signal, V+ signal, ramp signal VS and pulse signal SP is shown in FIG. 3. As shown in FIG. 3, the ramp-up period and the ramp down period are fixed, so the period of the pulse signal SP is fixed. In this case, the NMOS transistor 105 (shown in FIG. 1) will be switched at a fixed frequency regardless the loading condition of the fly-back type power converter. However, if the loading condition is in light load or in empty load, this design will waste much power and surely does not comply with the energy-saving requirement.
Therefore, there is a demand to provide an efficient PWM controller with adjustable output pulse frequency that can offer flexibility in selecting the pulse frequency according to the loading condition, to manage the power consumption of a power conversion application.